The present invention relates to semiconductor memory device manufacturing, and more particular to methods of forming dual workfunction high-performance support MOSFETs (metal oxide semiconductor field effect transistors) in an EDRAM (embedded dynamic random access memory) array.
Embedded DRAM applications demand both the utmost in high-performance CMOS (complementary metal oxide semiconductor) logic devices and high-density DRAM arrays. High-performance CMOS logic devices require low-resistance (on the order of 5 ohms/sq. or below) gate conductors and source/drain diffusions (salicidation), which drive processes that are costly and difficult to integrate with high-density DRAM processes. For example, salicided gates and source/drain regions greatly complicate the processes for forming array MOSFETs since the array MOSFETs need bitline contacts which are borderless to adjacent wordline conductors; also, salicided junctions in the array may result in increased current leakage of the memory device.
In a typical DRAM array, the wordlines need to be capped with an insulator, while in the supports the gate conductors must be exposed to allow the introduction of dual workfunction doping and salicidation. Conventional solutions to these integration problems require additional masking steps to remove the insulating gate cap from the support MOSFETs prior to the salicidation process.
Another problem encountered in prior art processes is the lithography steps used to simultaneously form support gates and wordlines: optimization of support gate lithography results in difficulties with defining wordlines in the array which are on a 2F pitch.
Yet another problem with prior art processes is in the formation of local interconnects. Specifically, in the prior art one of the metallization levels, i.e., the M0 level, is used for both the bitline and for forming local interconnects. In the present invention, the conventional M0 metal is not required since the bitlines and local interconnects are formed by the salicidation of polysilicon.
In view of the drawbacks mentioned hereinabove with prior art processes of forming dual workfunction high-performance support MOSFETs in EDRAM arrays, there is a need for developing new and improved methods of manufacturing the same. That is, new and improved methods are needed for integrating high-performance CMOS logic devices with dense array MOSFET DRAM cells.
One object of the present invention is to provide a method of manufacturing a dual workfunction high-performance support MOSFETIEDRAM array in which the need for additional masking steps to form the high-performance CMOS logic devices and borderless contacts are eliminated.
A further object of the present invention is to provide a method of manufacturing a dual workfunction high-performance support MOSFET/EDRAM array wherein the method does not share support gate conductor lithography with wordline lithography.
A still further object of the present invention is to provide a method of manufacturing a dual workfunction high-performance support MOSFETIEDRAM array wherein the gate conductor lithography is shared with the array bitline lithography step. Sharing of a single masking step for the support gate conductor and array bitlines results in the saving of a deep-UV mask and is less demanding due to its 3F pitch.
A yet further object of the present invention is to provide a method of manufacturing a dual workfunction high-performance support MOSFET/EDRAM array which does not use an M0 level for the local interconnect.
Another object of the present invention is to provide a dual workfunction high performance support MOSFET/EDRAM array in which a gate conductor guard ring is formed around the array region of the structure so as to avoid trapping of a stringer of polysilicon in the isolation region. The presence of the guard ring provides an internal protection scheme, which prevents the designer from placing a gate conductor across the isolation region.
An even further object of the present invention is to provide a dual workfunction high performance support MOSFET/EDRAM array comprising a local interconnect which is formed concurrently, and of the same low-resistance material, as the gate conductor in the array region.
These and other objects and advantages are achieved in the present invention by employing one of the following three processing schemes which are each capable of integrating high-performance CMOS logic devices with dense array MOSFET DRAM cells. It should be noted that the present invention contemplates the formation of vertical and planar MOSFET arrays, with vertical MOSFET arrays being more preferable than planar MOSFET arrays. Therefore, although the following is specific to vertical MOSFET arrays, the processing steps used each of the three embodiments can be used in making planar MOSFET arrays.
In accordance with a first embodiment of the present invention, a process of forming a dual workfunction high-performance support MOSFET/EDRAM vertical (or planar) array memory structure having a gate conductor guard ring formed around the array region is provided. The gate conductor guard ring is a consequence of a ground rule that guarantees that a strip of gate conductor polysilicon remains above the isolation region surrounding the array.
Specifically, the first embodiment of the present invention comprises the steps of:
(a) providing a memory structure having at least one array region and at least one support region, wherein said at least one array region and said at least one support region are separated by an isolation region, wherein said at least one array region includes a plurality of dynamic random access memory (DRAM) cells embedded in a substrate, wherein adjacent DRAM cells are connected to each other through bitline diffusion regions which are capped with an oxide capping layer;
(b) forming a patterned nitride layer on all exposed surfaces in said at least one array region and on a portion of said isolation region;
(c) forming a gate oxide on said substrate in said at least one support region;
(d) forming a stack comprising a first polysilicon layer and a dielectric capping layer on all exposed surfaces of said memory structure;
(e) removing said dielectric capping layer, said first polysilicon layer and said nitride layer from said at least one array region;
(f) forming wordlines over said plurality of DRAM cells in said at least one array region;
(g) forming spacers on exposed sidewalls of said wordlines in said at least one array region as well as on exposed sidewalls of said stack remaining in said structure;
(h) forming a block mask over the at least one support region and at least a portion of one of said DRAM cells that is adjacent to said isolation region, whereby said block mask does not cover said oxide capping layer;
(i) removing said oxide capping layer over said bitline diffusion regions and stripping said block mask;
(j) forming a patterned second polysilicon layer over the at least one array region and said stack which is present on said isolation region, and removing said dielectric capping layer in said at least one support region;
(k) forming a doped glass material layer over all surfaces in said at least one array region and said at least one support region;
(l) patterning said doped glass material layer so as to form hard masks in said at least one array region and said at least one support region, whereby said hard mask in said at least one array region defines a bitline of the memory structure and said hard mask in said at least one support region defines a support gate region;
(m) removing exposed second polysilicon layer from said at least one array region and said isolation region, while simultaneously removing exposed portions of said first polysilicon layer in said at least one support region, whereby a gate conductor guard ring is formed on said isolation region and said support gate region is formed in said at least one support region;
(n) removing said hard masks from said at least one array region and from said at least one support region and forming a screen oxide layer on any exposed silicon surfaces;
(o) forming source and drain regions about said support gate region; and
(p) removing oxide overlying said bitline, support gate region, and source and drain regions so as to expose silicon surfaces and saliciding the exposed silicon surfaces so as to provide salicide regions over said bitline, said gate region and said source and drain regions.
A further processing step of the first embodiment of the present invention includes forming a patterned dielectric having via openings overlying the memory structure provided in step (p) above. The via openings allow for the formation of contacts to the support gate region.
In a second embodiment of the present invention, an array/support transition region, which does not contain a gate conductor guard ring over the isolation region around the perimeter of the array, is provided. In this embodiment, the block mask used to protect areas outside of the array during the removal of the oxide layer in the first embodiment is eliminated. Furthermore, the dielectric cap protecting the support polysilicon is removed early in this embodiment. These changes result in improved planarity, eliminating the need for planarizing the doped glass layer. Thus, the support gate stack height, which needs to be patterned, is significantly reduced resulting in improved linewidth control.
The second embodiment of the present invention comprises the steps of:
(a) providing a memory structure having at least one array region and at least one support region, wherein said at least one array region and said at least one support region are separated by an isolation region, wherein said at least one array region includes a plurality of dynamic random access memory (DRAM) cells embedded in a substrate, wherein adjacent DRAM cells are connected to each other through bitline diffusion regions which are capped with an oxide capping layer;
(b) forming a patterned nitride layer on all exposed surfaces in said at least one array region and on a portion of said isolation region;
(c) forming a gate oxide on said substrate in said at least one support region;
(d) forming a stack comprising a first polysilicon layer and a dielectric capping layer on all exposed surfaces of said memory structure;
(e) removing said dielectric capping layer, said first polysilicon layer and said nitride layer from said at least one array region;
(f) forming wordlines over said plurality of DRAM cells in said at least one array region;
(g) forming spacers on exposed sidewalls of said wordlines in said at least one array region as well as on exposed sidewalls of said stack remaining in said structure;
(h) anisotropically etching said memory structure so as to remove said oxide capping layer thereby exposing said bitline diffusion regions in said at least one array region, while simultaneously removing said dielectric capping layer over said isolation region and in said at least one support region;
(i) depositing an undoped layer of polysilicon over all exposed surfaces of said memory structure;
(j) patterning said undoped layer of polysilicon so as to simultaneously form a bitline in said at least one array region and a gate region in said at least one support region;
(k) forming a screen oxide layer on any exposed silicon surfaces;
(l) forming sidewall spacers about said gate region;
(m) forming source and drain regions about said gate region; and
(n) removing oxide overlying said bitline, gate region, and source and drain regions so as to expose silicon surfaces and saliciding said exposed silicon surfaces so as to provide salicide regions over said bitline, said gate region and said source and drain regions.
A further-processing step of the second embodiment of the present invention includes forming a patterned dielectric having via openings overlying the memory structure provided in step (n) above. The via openings allow for the formation of contacts to the support gate region.
The third embodiment of the present invention provides a method for forming a local interconnect wiring level in a dual workfunction high-performance MOSFET/EDRAM array. Specifically, the third embodiment of the present invention comprises the steps of:
(a) providing a memory structure having at least one array region and at least one support region, wherein said at least one array region and said at least one support region are separated by an isolation region, wherein said at least one array region includes a plurality of dynamic random access memory (DRAM) cells embedded in a substrate, wherein adjacent DRAM cells are connected to each other through bitline diffusion regions which are capped with an oxide capping layer;
(b) forming a patterned nitride layer on all exposed surfaces in said at least one array region and on a portion of said isolation region;
(c) forming a gate oxide on said substrate in said at least one support region;
(d) forming a stack comprising a first polysilicon layer and a dielectric capping layer on all exposed surfaces of said memory structure;
(e) removing said dielectric capping layer, said first polysilicon layer and said nitride layer from said at least one array region and a portion of said at least one support region;
(f) doping a portion of said substrate in said support region so as to form a diffusion region for subsequent formation of a local interconnect contact thereon;
(g) forming wordlines over said plurality of DRAM cells in said at least one array region, while simultaneously forming a local interconnect in said at least one support region above said diffusion region, wherein said wordlines and said local interconnect are composed of the same material;
(h) forming spacers on exposed sidewalls of said wordlines in said at least one array region, and said local interconnect and remaining stack in said at least one support region, said remaining stack defining a support gate region of said structure;
(i) removing any exposed oxide over said bitline diffusion regions;
(j) forming a patterned second polysilicon layer over the at least said at least one array region and said stack which is overlaying said isolation region, and removing said dielectric capping layer in said at least one support region;
(k) forming a doped glass material layer over all surfaces in said at least one array region and said at least one support region;
(l) patterning said doped glass material layer so as to form a hard mask in said at least one array region, whereby said hard mask in said at least one array region defines a bitline of the memory structure;
(m) removing said hard mask from said at least one array region and forming an oxide layer on all exposed silicon surfaces;
(n) forming source and drain regions about said gate region; and
(p) removing oxide overlying said bitline, support gate region, and source and drain regions so as to expose said silicon surfaces and saliciding said silicon surfaces so as to provide salicide regions over said bitline, said support gate region and said source and drain-regions.
A further processing step of the third embodiment of the present invention includes forming a patterned dielectric having via openings overlying the memory structure provided in step (p) above. The via openings allow for the formation of contacts to the support gate region.
In addition to the above methods, the present invention also contemplates various dual workfunction high-performance support MOSFET/EDRAM array. In one memory structure of the present invention, a guard ring is present around the array region. In another memory cell of the present invention, a local interconnect, which is composed of the same material as that of the wordline, is provided. In yet another memory structure of the present invention, vertical DRAMs are present. In an even further embodiment of the present invention, planar DRAMs are present.